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The earlier the signal integrity (SI) issues are addressed in a circuit board design, the more efficient the design will be, thus avoiding the need to add new termination devices after the board design is complete. There are a number of tools and resources available for SI design planning, but we will now explore the central issue of signal integrity and a few ways to address the SI problem.
1.The SI Problem
As IC output switching speeds increase, signal integrity problems are encountered in almost all designs, regardless of signal period. Even if you have not encountered SI problems in the past, you will certainly encounter signal integrity problems in the future as the frequency of circuit operation increases.
Signal integrity problems are primarily signal overshoot and damped oscillations, which are functions of the IC drive amplitude and hopping time. That is, even if the topology of the wiring is unchanged, if the chip speed becomes fast enough, the existing design will become critical or stop working. We use two examples to illustrate that signal integrity design is unavoidable.
Example one: In communications, where leading edge telecoms companies are producing high speed boards (above 500MHz) for voice and data switching, cost is not particularly important and multilayer boards can be used as much as possible. Such boards can be fully grounded and easily constructed into power loops, and as many discrete terminations as required, but the design must be correct and not critical.
SI and EMC experts carry out simulations and calculations before routing the circuit boards. The boards can then be designed to follow a very strict set of design rules, and where there is doubt, new terminations can be added in order to obtain as much SI safety margin as possible. SI problems can be avoided through the use of controlled impedance termination wires for circuit boards that are subject to problems during actual operation. In short, the SI problem can be solved by over-standard design.
Example two: From cost considerations, circuit boards are usually limited to four layers (the inner two layers are the power layer and grounding layer). This greatly limits the usefulness of impedance control. In addition, fewer layers will increase crosstalk, and signal line spacing must be minimised in order to place more printed wires. On the other hand, design engineers must use the latest and best CPU, memory, and video bus designs, and these designs must take SI issues into consideration.
With regard to cabling, topology and end-channels, it is important to consider SI issues. Topologies and termination channels, engineers can usually get a lot of advice from CPU manufacturers, however, these design guidelines also need to be integrated with the manufacturing process. To a large extent, the board designer's job is more difficult than the telecom designer's because there is little room for additional impedance control and termination devices. Incomplete signals must be fully investigated and resolved, while ensuring that the product is designed to meet the deadline.
Circuit Board Designs
The following section describes the SI design criteria that are common to the circuit board design process.
2.Preparation before board design
Before the design begins, it is important to think about and determine the design strategy, which can guide such as component selection. Process selection and board production cost control work. In the case of SI, it is important to conduct research in advance to develop planning or design criteria to ensure that the design results in no significant SI problems. Crosstalk or timing problems. Some of the design criteria can be provided by the IC manufacturer, however, there are limitations to the criteria provided by the chip supplier (or your own design criteria), and it may not be possible to design a board that meets the SI requirements based on such criteria. If design rules were easy, there would be no need for a design engineer.
In most cases, these issues will affect the boards you are designing (or considering designing) before the actual wiring is done, which is worthwhile if the number of boards is large.
3.Board Layers
Some project teams have a lot of autonomy in determining the number of PCB layers, while others don't, so it's important to know where you stand. Talking to manufacturing and cost analysis engineers can identify board layer errors, and this is also a good opportunity to find out about board manufacturing tolerances. For example, if you specify a layer to be 50Ω impedance controlled, how can the manufacturer measure and ensure this value?
Other important questions include: What are the expected manufacturing tolerances? What are the expected insulation constants on the board? What are the allowable tolerances for line width and spacing? What are the allowable errors in the thickness and spacing of the grounding and signalling layers? All of this information can be used in the prewiring stage.
Based on the above data, you can select the layer. Note that almost every PCB inserted into other boards or backplanes has a thickness requirement, and most board manufacturers have fixed thickness requirements for the different types of layers they can make, which will greatly constrain the number of final layers. You may be tempted to work closely with the manufacturer to define the number of layers. Impedance control tools should be used to generate target impedance ranges for the different layers, taking into account the manufacturing tolerances provided by the manufacturer and the effect of neighbouring wiring.
Ideally, all high-speed nodes should be routed on the inner impedance control layer (e.g., stripline) for signal integrity, but in practice, engineers must often use the outer layer for all or some of the high-speed nodes. To optimise SI and keep the board decoupled, ground/power pairs should be placed wherever possible. If there is only one ground/power pair, you have to make do. If there is no power layer at all, by definition you may have an SI problem. You may also encounter situations where it is difficult to simulate or model the performance of the board without defining the return path of the signal.
4.Crosstalk and Impedance Control
Coupling from neighbouring signal lines will cause crosstalk and change the impedance of the signal lines. An analysis of the coupling of adjacent parallel signal lines may determine the ‘safe’ or expected spacing (or length of parallel wiring) between signal lines or between various types of signal lines. For example, if you want to limit crosstalk from a clock to a data signal node to less than 100mV, but want the signal alignments to remain parallel, you can find the minimum allowable spacing between the signals at any given layout by calculation or simulation. Also, if the design contains nodes where impedance is important (either clocks or dedicated high-speed memory architectures), you will have to place the wiring on one (or more) layers to get the desired impedance.
5. Important high-speed nodes
Delay and time lag are critical factors that must be considered in clock routing. Because of the stringent timing requirements, such nodes often must be terminated to achieve the best SI quality. It is important to identify these nodes in advance and to plan for the time required to adjust component placement and routing in order to adjust the signal integrity design guidelines.
6. Board Technology Selection
Different driver technologies are appropriate for different tasks. Is the signal point-to-point or point-to-multiple tap? Is the signal coming out of the board or staying on the same board? What are the allowable time lag and noise margins? As a general guideline for signal integrity design, the slower the conversion speed, the better the signal integrity. There is no reason to use a 500ps rise time for a 50MHz clock. A 2-3ns swing rate control device needs to be fast enough to guarantee SI quality and help address issues like output synchronous switching (SSO) and electromagnetic compatibility (EMC).
The superiority of driver technology can be found in new FPGA programmable design techniques or user-defined ASICs. With these custom or semi-custom devices, you have a great deal of leeway in selecting drive amplitude and speed. Early in the design phase, it is important to meet the FPGA or ASIC design time requirements and determine the appropriate output selection, including pin selection if possible.
At this stage of the design, appropriate simulation models are obtained from the IC supplier. In order to effectively cover the SI simulation, you will need an SI simulation program and a corresponding simulation model (possibly an IBIS model).
Finally, in the pre-routing and routing phase you should establish a set of design guidelines, which include: target layer impedance. Wire spacing. Preferred device technology. Important node topology and termination planning.
7. PCB Pre-Wiring Stage
The basic process of pre-circuit SI planning is to first define the input parameter ranges (drive amplitude, impedance, and voltage). Impedance. Tracking speed) and the range of possible topologies (min/max lengths, short lengths, etc.). Then run each possible simulation combination, analyse the timing and SI simulation results, and finally find an acceptable range of values.
Next, the working range is interpreted as a PCB routing constraint. Various software tools can be used to perform this type of ‘clean-up’ preparation, and the routing programme is able to handle such routing constraints automatically. For most users, timing information is actually more important than the SI results, and the results of the interconnect simulation can be used to change the routing and thus adjust the timing of the signal path.
In other applications, this process can be used to identify pins or device layouts that are incompatible with the system timing guidelines. In this case, it is possible to completely identify nodes that need to be manually wired or nodes that do not need to be terminated. For programmable devices and ASICs, it is also possible to adjust the choice of output drivers in order to improve the SI design or avoid discretely terminated devices.
circuit board design
8.SI Simulation after PCB Layout
In general, it is very difficult to guarantee that SI or timing problems will not occur after the actual wiring has been completed by the SI design guidelines.Even if the design is guided by the guidelines, unless you are able to automatically check the design on a continuous basis, there is no guarantee that the design will comply with the guidelines, and problems will inevitably occur.Post-route SI simulation checks will allow design rules to be systematically broken or changed, but this is only necessary due to cost considerations or stringent routing requirements.
It is now possible to simulate high-speed digital PCBs and even multi-board systems using an SI simulation engine that automatically masks SI problems and generates accurate ‘pin-to-pin’ delay parameters. As long as the input signals are good enough, the simulation results will be just as good. This makes the accuracy of the device model and board fabrication parameters a critical factor in determining simulation results. Many design engineers will simulate ‘minimum’ and ‘maximum’ design corners and then use the information to solve problems and adjust yields.
9.Board Manufacturing Stage
While the above measures ensure the quality of the SI design of the boards, after the boards are assembled, it is still necessary to place the boards on a test bench and compare the real boards with the simulated expected results using oscilloscope or TDR (Time Domain Reflectometer) measurements. These measurements will help you to improve your model and manufacturing parameters so that you can make better (and less constrained) decisions in your next pre-design study.
10.Model Selection
Much has been written about model selection, and engineers performing static timing verification may have noticed that it is difficult to build a model despite all the data available from device datasheets. The opposite is true for SI simulation models, where the model is easy to build, but the model data is difficult to obtain. In essence, the only reliable source of SI model data is the IC supplier, who must work in tandem with the design engineer. The IBIS modelling standard provides a consistent data carrier, but IBIS models are costly to build and quality assure, and IC suppliers still need to be driven by market demand for this investment, with board manufacturers possibly being the only demand-side market.
11.Future Trends in PCB Technology
Imagine a system where all outputs can be adjusted to match the wiring impedance or load of the receiving circuit. Such a system is easy to test, and SI problems can be solved by programming, or by adjusting the board to meet SI requirements according to the IC's specific process distribution, which allows for larger design tolerances or a wider range of hardware configurations.
Currently, the industry is also focusing on an SI device technology, many of which include designed termination devices (e.g., LVDS) and automatic programmable output strength control and dynamic auto termination functions. Board designs using these technologies can achieve excellent SI quality, but most of these technologies are too different from standard CMOS or TTL logic circuits and do not work well with existing analogue models. not work well with existing analogue models.
Here too, EDA companies are joining the circuit board design arena, where a lot of work has been done to solve SI problems in the early stages of design, and in the future, SI problems can be solved with automated tools without the need for an SI expert. Although the technology has not yet reached that level, new design methods are being explored, and the technology for starting board design from ‘SI and timing routing’ is still evolving, and new board design technologies are expected to be born in the next few years.