One-stop service for electronic manufacturing, We focus on PCB prototype fabrication, PCBA assembly, ODM services, and electronic product design.
A Trustworthy PCB and Electronic Manufacturing Enterprise! Contact Us
PCB News

PCB News - How to extract multi-layer circuit board stacks?

PCB News

PCB News - How to extract multi-layer circuit board stacks?

How to extract multi-layer circuit board stacks?
2019-08-01
View:1105
Author:iPCB

Nowadays, circuit board designs with more than 4 layers are commonly used in high-speed and complex circuit designs. How to extract suitable layers? This article analyzes the commonly used multi-layer circuit board stacking.


4layer PCB design scheme

1. Stacking scheme one: TOP GND2、PWR3、BOTTOM

This scheme is currently the mainstream choice for four layers in the industry. There is a complete ground plane below the main device surface (TOP), which serves as the wiring layer. When setting the layer thickness, the thickness of the core board between the ground plane layer and the power plane layer should not be too thick to reduce the distributed impedance of the power and ground planes and ensure the filtering effect of the planar capacitance.


2. Stacking scheme 2: TOP PWR2、GND3、BOTTOM

If the main component surface is designed at the BOTTOM layer or the key signal lines are at the BOTTOM layer, the third layer needs to be arranged on a complete ground plane. When setting the layer thickness, the thickness of the core board between the ground plane layer and the power plane layer should not be too thick.


3. Stacking scheme three: GND1, S2, S3, GND4/PWR4

This scheme is usually applied in the design of interface filter boards and backboards. Due to the absence of a power plane on the entire board, GND and PGND are arranged on the layer and fourth layer respectively. Only a small number of short lines are allowed to be laid on the surface layer (TOP layer). Similarly, we lay copper on the S02 and S03 wiring layers to ensure the reference plane of the surface wiring and control the symmetry of the stacking.


Multi-layer circuit board

Multi-layer circuit board

6layer PCB design scheme

1. Stacking scheme one: TOP, GND2, S3, PWR4, GND5, BOTTOM. This scheme is currently the mainstream 6-layer selection scheme in the industry, with 3 wiring layers and 3 reference planes. The thickness of the core board between the fourth and fifth layers should not be too thick in order to achieve lower transmission line impedance. The low impedance characteristic can improve the decoupling effect of the power supply.

The third layer is the wiring layer, where high-risk lines such as clock lines must be laid to ensure signal integrity and resist EMI energy. The bottom layer is the second best wiring layer. The top layer is a wiring layer.


2. Stacking scheme two: TOP, GND2, S3, S4, PWR5, BOTTOM. When there are too many traces on the circuit board and the three wiring layers cannot be arranged, this stacking scheme can be used. This scheme has four wiring layers and two reference planes, but there are two signal layers sandwiched between the power plane and the ground plane, and there is no power decoupling effect between the power plane and the ground plane.

Due to its proximity to the ground plane, the third layer is a wiring layer and should be equipped with high-risk lines such as clocks. The first, fourth, and sixth layers are wiring layers.


3. Stacking scheme three: TOP, S2, GND3, PWR4, S5, BOTTOM. This scheme also has four wiring layers and two reference planes. The power plane/ground plane of this structure adopts a small spacing structure, which can provide lower power impedance and better power decoupling effect.

The top and bottom layers are poor wiring layers. The second layer near the ground plane is the wiring layer, which can be used to lay high-risk signal lines such as clocks. Under the condition of ensuring the RF same current path, the 5th layer can also be used as the wiring layer for other high-risk signal lines. Cross wiring should be used for the first and second layers, as well as the fifth and sixth layers.


8layer PCB design scheme

1. Stacking scheme one: TOP, GND2, S3, GND4, PWR5, S6, GND7, BOTTOM This scheme is the main layer setting scheme for the current 8 layer circuit board in the industry, with 4 wiring layers and 4 reference planes. The signal integrity and EMC characteristics of this stacked structure are both good, and the power decoupling effect can be obtained.

The top and bottom layers are EMI playable layers. The adjacent layers of the third and sixth layers are both reference planes, which are the wiring layers. The third layer is a routing layer as both adjacent layers are on the ground plane. The thickness of the core PCB board between the fourth and fifth layers should not be too thick in order to obtain lower transmission line impedance, which can improve the decoupling effect of the power supply.


2. Stacking scheme two: TOP, GND2, S3, PWR4, GND5, S6, PWR7, BOTTOM. Compared with scheme one, this scheme is suitable for situations where there are many types of power sources that cannot be handled by one power plane. The third layer is the wiring layer. The main power supply should be arranged on the 4th floor and can be adjacent to the main ground.

The power plane on the 7th floor is a segmented power supply. In order to improve the decoupling effect of the power supply, copper pipes should be laid on the bottom floor. In order to balance the circuit board and reduce warpage, the top layer also needs to be covered with copper flooring.


3. Stacking scheme three: TOP, S2, GND3, S4, S5, PWR6, S7, BOTTOM. This scheme has 6 wiring layers and 2 reference planes. The decoupling characteristics of this stacked structure power supply are poor, and the EMI suppression effect is also poor. The top and bottom layers are wiring layers with poor EMI characteristics. The second and fourth layers adjacent to the ground plane are the wiring layers for clock lines, and cross wiring should be used.

The 5th and 7th layers adjacent to the power plane are acceptable wiring layers. This scheme is usually used for 8-layer backplane designs with fewer surface mount devices. Since the surface only has sockets, the surface can be extensively covered with copper.