sales@ipcb.com
In high-speed digital and RF PCB design, engineers often focus heavily on substrate selection, precise 50Ω impedance control, and ground plane integrity. However, via structure optimization is frequently overlooked. In high-frequency GHz applications, vias create the most severe impedance discontinuities in signal channels, becoming the dominant source of return loss degradation, insertion loss drop, and signal integrity failure. This explains why many perfectly simulated PCB layouts still fail physical testing after fabrication.
At low frequencies, vias act as simple layer-to-layer connections with negligible parasitic effects. Once signal rates exceed 5 Gbps or operating frequencies rise above 5 GHz, vias no longer behave as ideal conductors. Their physical structure forms a complex parasitic LC network. Unoptimized vias commonly cause RF oscillation, excessive high-frequency loss, and closed eye diagrams in high-speed links. This article presents a concise, data-driven guideline for via selection based on industry manufacturing standards and HFSS simulation results.
1.High-Frequency Parasitic Characteristics of PCB Vias
High-speed and RF design failures related to vias stem from three core parasitic effects.
First, parasitic series inductance. The metallic barrel of a via acts as a narrow inductive conductor. A standard 1.6 mm FR4 through-hole with 0.3 mm diameter produces 1.0–1.2 nH inductance. At 10 GHz, the reactance exceeds 70 Ω, severely breaking 50Ω impedance matching. For thick boards of 4–6 mm, unprocessed through-hole stubs push inductance above 2.0 nH, generating strong high-frequency attenuation.
Second, parasitic shunt capacitance. Via pads and adjacent ground anti-pad areas form parallel-plate capacitance, typically ranging from 0.15 pF to 0.35 pF for standard RF vias. At 10 GHz, this capacitance significantly attenuates high-frequency signal components, prolongs rise time, and reduces system bandwidth. Multiple cascaded vias create a low-pass filtering effect that deteriorates high-speed signal quality.
Third, impedance discontinuity. A typical through-hole reduces local impedance from 50Ω to 28–35Ω. Simulation results show that this abrupt change causes return loss to drop to -10 dB ~ -14 dB at 10 GHz, reflecting nearly 40% of signal energy and severely degrading RF and high-speed link performance.
2. Comparison of Four Common Via Types
Via structure determines high-frequency performance far more than minor dimensional adjustments. Each via type presents distinct parasitic characteristics and application boundaries.
Through-hole vias are low-cost and process-friendly but exhibit poor high-frequency performance. Full-board penetration creates long residual stubs, forming resonant cavities between 8–12 GHz on thick boards and causing 2–5 dB insertion loss degradation. They are only suitable for low-frequency circuits below 2 GHz and power/ground connections, not for high-speed or RF signal paths.
Blind and buried vias provide superior high-frequency performance. Blind vias connect only outer layers to inner layers, reducing effective via length and limiting inductance to 0.4–0.8 nH. Buried vias are completely embedded inside the stackup, eliminating stub resonance and surface radiation. Both structures stabilize return loss below -20 dB at 10 GHz. The main disadvantage is higher cost due to multi-lamination processes, making them suitable only for millimeter-wave and 25 Gbps+ high-end designs.
Back-drilled vias offer the best cost-performance balance for mass production. By mechanically removing redundant through-hole stubs and controlling residual stub length within 0.2 mm, parasitic inductance is drastically reduced. On 6 mm thick high-frequency boards, back-drilling improves 10 GHz return loss from -11 dB to -22 dB and optimizes insertion loss by more than 0.8 dB. With only 10–20% cost increase compared to standard through-holes, this is the optimal solution for 3–15 GHz RF modules and 10 Gbps high-speed links.
HDI microvias feature ultra-small diameters below 0.15 mm with minimal parasitic inductance of 0.1–0.3 nH. They are designed for 50 Gbps+ ultra-high-speed interconnects but require advanced fabrication and yield lower production rates on thick boards, making them unnecessary for conventional RF projects.
3. High-Frequency Via Dimensional Design Rules
Reasonable dimension matching further minimizes parasitic effects while ensuring manufacturability.
Hole diameter: 0.25–0.3 mm is the industry sweet spot. Smaller diameters reduce inductance but increase tool breakage risk on thick boards; larger diameters introduce obvious high-frequency deterioration.
Pad size: On the premise of soldering reliability, pads should be minimized. A 0.3 mm hole matched with 0.5–0.6 mm pads maintains a safe 0.1–0.15 mm annular ring and effectively suppresses parasitic capacitance growth.
Anti-pad size: This is the most impactful yet easily overlooked parameter. Setting the anti-pad 0.15–0.2 mm larger than the pad significantly reduces pad-to-ground capacitance. HFSS tests confirm this optimization reduces parasitic capacitance by approximately 40% and improves return loss by 6–8 dB. Excessively large anti-pads should be avoided to prevent ground plane fragmentation and distorted return current paths.
4. Key Design Guidelines for High-Speed & RF Vias
Several verified design rules ensure consistent high-frequency performance.
First,stub length must be controlled within 0.2 mm. Residual stubs cause in-band resonance; limiting stub length shifts resonant points beyond 18 GHz, covering most commercial RF bands.
Second, signal vias require surrounding grounded via fences. Ground vias placed at λ/10 intervals provide continuous return paths, reduce loop inductance, and suppress EMI and crosstalk.
Third, differential vias must maintain strict symmetry. Asymmetry in diameter, pad size, anti-pad dimension, or via height introduces phase offset and common-mode noise, degrading differential signal performance by over 3 dB.
Fourth, high-frequency simulation must include complete 3D via models. Ignoring via structures leads to 5–10 dB deviation between simulation and actual measurement.
5. Conclusion
In high-speed digital and RF PCB design, vias are critical high-frequency components rather than simple mechanical openings. Each via type and dimension directly affects impedance continuity, parasitic resonance, and overall signal integrity. Through-holes serve low-cost low-frequency applications, back-drilled vias deliver optimal cost-performance for mainstream high-frequency thick-board designs, and blind/buried/microvias are reserved for ultra-high-speed and millimeter-wave scenarios. Accurate via selection based on frequency, stackup, and cost constraints is essential for reliable, high-yield, and high-performance PCB designs.